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<div class="title">D:/123/stm32f4_blink_led-1.2.2-120323/inc/core_cm4.h</div>  </div>
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<a href="core__cm4_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/**************************************************************************/</span>
<a name="l00023"></a>00023 <span class="preprocessor">#if defined ( __ICCARM__ )</span>
<a name="l00024"></a>00024 <span class="preprocessor"></span><span class="preprocessor"> #pragma system_include  </span><span class="comment">/* treat file as system include file for MISRA check */</span>
<a name="l00025"></a>00025 <span class="preprocessor">#endif</span>
<a name="l00026"></a>00026 <span class="preprocessor"></span>
<a name="l00027"></a>00027 <span class="preprocessor">#ifdef __cplusplus</span>
<a name="l00028"></a>00028 <span class="preprocessor"></span> <span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {
<a name="l00029"></a>00029 <span class="preprocessor">#endif</span>
<a name="l00030"></a>00030 <span class="preprocessor"></span>
<a name="l00031"></a>00031 <span class="preprocessor">#ifndef __CORE_CM4_H_GENERIC</span>
<a name="l00032"></a>00032 <span class="preprocessor"></span><span class="preprocessor">#define __CORE_CM4_H_GENERIC</span>
<a name="l00033"></a>00033 <span class="preprocessor"></span>
<a name="l00034"></a>00034 
<a name="l00064"></a>00064 <span class="comment">/*******************************************************************************</span>
<a name="l00065"></a>00065 <span class="comment"> *                 CMSIS definitions</span>
<a name="l00066"></a>00066 <span class="comment"> ******************************************************************************/</span>
<a name="l00075"></a>00075 <span class="comment">/*  CMSIS CM4 definitions */</span>
<a name="l00076"></a>00076 <span class="preprocessor">#define __CM4_CMSIS_VERSION_MAIN  (0x02)                                                       </span>
<a name="l00077"></a>00077 <span class="preprocessor">#define __CM4_CMSIS_VERSION_SUB   (0x10)                                                       </span>
<a name="l00078"></a>00078 <span class="preprocessor">#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN &lt;&lt; 16) | __CM4_CMSIS_VERSION_SUB) </span>
<a name="l00080"></a>00080 <span class="preprocessor">#define __CORTEX_M                (0x04)                                                       </span>
<a name="l00083"></a>00083 <span class="preprocessor">#if   defined ( __CC_ARM )</span>
<a name="l00084"></a>00084 <span class="preprocessor"></span><span class="preprocessor">  #define __ASM            __asm                                      </span>
<a name="l00085"></a>00085 <span class="preprocessor">  #define __INLINE         __inline                                   </span>
<a name="l00087"></a>00087 <span class="preprocessor">#elif defined ( __ICCARM__ )</span>
<a name="l00088"></a>00088 <span class="preprocessor"></span><span class="preprocessor">  #define __ASM           __asm                                       </span>
<a name="l00089"></a>00089 <span class="preprocessor">  #define __INLINE        inline                                      </span>
<a name="l00091"></a>00091 <span class="preprocessor">#elif defined ( __GNUC__ )</span>
<a name="l00092"></a>00092 <span class="preprocessor"></span><span class="preprocessor">  #define __ASM            __asm                                      </span>
<a name="l00093"></a>00093 <span class="preprocessor">  #define __INLINE         inline                                     </span>
<a name="l00095"></a>00095 <span class="preprocessor">#elif defined ( __TASKING__ )</span>
<a name="l00096"></a>00096 <span class="preprocessor"></span><span class="preprocessor">  #define __ASM            __asm                                      </span>
<a name="l00097"></a>00097 <span class="preprocessor">  #define __INLINE         inline                                     </span>
<a name="l00099"></a>00099 <span class="preprocessor">#endif</span>
<a name="l00100"></a>00100 <span class="preprocessor"></span>
<a name="l00102"></a>00102 <span class="preprocessor">#if defined ( __CC_ARM )</span>
<a name="l00103"></a>00103 <span class="preprocessor"></span><span class="preprocessor">  #if defined __TARGET_FPU_VFP</span>
<a name="l00104"></a>00104 <span class="preprocessor"></span><span class="preprocessor">    #if (__FPU_PRESENT == 1)</span>
<a name="l00105"></a>00105 <span class="preprocessor"></span><span class="preprocessor">      #define __FPU_USED       1</span>
<a name="l00106"></a>00106 <span class="preprocessor"></span><span class="preprocessor">    #else</span>
<a name="l00107"></a>00107 <span class="preprocessor"></span><span class="preprocessor">      #warning &quot;Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)&quot;</span>
<a name="l00108"></a>00108 <span class="preprocessor"></span><span class="preprocessor">      #define __FPU_USED       0</span>
<a name="l00109"></a>00109 <span class="preprocessor"></span><span class="preprocessor">    #endif</span>
<a name="l00110"></a>00110 <span class="preprocessor"></span><span class="preprocessor">  #else</span>
<a name="l00111"></a>00111 <span class="preprocessor"></span><span class="preprocessor">    #define __FPU_USED         0</span>
<a name="l00112"></a>00112 <span class="preprocessor"></span><span class="preprocessor">  #endif</span>
<a name="l00113"></a>00113 <span class="preprocessor"></span>
<a name="l00114"></a>00114 <span class="preprocessor">#elif defined ( __ICCARM__ )</span>
<a name="l00115"></a>00115 <span class="preprocessor"></span><span class="preprocessor">  #if defined __ARMVFP__</span>
<a name="l00116"></a>00116 <span class="preprocessor"></span><span class="preprocessor">    #if (__FPU_PRESENT == 1)</span>
<a name="l00117"></a>00117 <span class="preprocessor"></span><span class="preprocessor">      #define __FPU_USED       1</span>
<a name="l00118"></a>00118 <span class="preprocessor"></span><span class="preprocessor">    #else</span>
<a name="l00119"></a>00119 <span class="preprocessor"></span><span class="preprocessor">      #warning &quot;Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)&quot;</span>
<a name="l00120"></a>00120 <span class="preprocessor"></span><span class="preprocessor">      #define __FPU_USED       0</span>
<a name="l00121"></a>00121 <span class="preprocessor"></span><span class="preprocessor">    #endif</span>
<a name="l00122"></a>00122 <span class="preprocessor"></span><span class="preprocessor">  #else</span>
<a name="l00123"></a>00123 <span class="preprocessor"></span><span class="preprocessor">    #define __FPU_USED         0</span>
<a name="l00124"></a>00124 <span class="preprocessor"></span><span class="preprocessor">  #endif</span>
<a name="l00125"></a>00125 <span class="preprocessor"></span>
<a name="l00126"></a>00126 <span class="preprocessor">#elif defined ( __GNUC__ )</span>
<a name="l00127"></a>00127 <span class="preprocessor"></span><span class="preprocessor">  #if defined (__VFP_FP__) &amp;&amp; !defined(__SOFTFP__)</span>
<a name="l00128"></a>00128 <span class="preprocessor"></span><span class="preprocessor">    #if (__FPU_PRESENT == 1)</span>
<a name="l00129"></a>00129 <span class="preprocessor"></span><span class="preprocessor">      #define __FPU_USED       1</span>
<a name="l00130"></a>00130 <span class="preprocessor"></span><span class="preprocessor">    #else</span>
<a name="l00131"></a>00131 <span class="preprocessor"></span><span class="preprocessor">      #warning &quot;Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)&quot;</span>
<a name="l00132"></a>00132 <span class="preprocessor"></span><span class="preprocessor">      #define __FPU_USED       0</span>
<a name="l00133"></a>00133 <span class="preprocessor"></span><span class="preprocessor">    #endif</span>
<a name="l00134"></a>00134 <span class="preprocessor"></span><span class="preprocessor">  #else</span>
<a name="l00135"></a>00135 <span class="preprocessor"></span><span class="preprocessor">    #define __FPU_USED         0</span>
<a name="l00136"></a>00136 <span class="preprocessor"></span><span class="preprocessor">  #endif</span>
<a name="l00137"></a>00137 <span class="preprocessor"></span>
<a name="l00138"></a>00138 <span class="preprocessor">#elif defined ( __TASKING__ )</span>
<a name="l00139"></a>00139 <span class="preprocessor"></span>    <span class="comment">/* add preprocessor checks to define __FPU_USED */</span>
<a name="l00140"></a>00140 <span class="preprocessor">    #define __FPU_USED         0</span>
<a name="l00141"></a>00141 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00142"></a>00142 <span class="preprocessor"></span>
<a name="l00143"></a>00143 <span class="preprocessor">#include &lt;stdint.h&gt;</span>                      
<a name="l00144"></a>00144 <span class="preprocessor">#include &lt;<a class="code" href="core__cm_instr_8h.html" title="CMSIS Cortex-M Core Instruction Access Header File.">core_cmInstr.h</a>&gt;</span>                
<a name="l00145"></a>00145 <span class="preprocessor">#include &lt;<a class="code" href="core__cm_func_8h.html" title="CMSIS Cortex-M Core Function Access Header File.">core_cmFunc.h</a>&gt;</span>                 
<a name="l00146"></a>00146 <span class="preprocessor">#include &lt;<a class="code" href="core__cm4__simd_8h.html" title="CMSIS Cortex-M4 SIMD Header File.">core_cm4_simd.h</a>&gt;</span>               
<a name="l00148"></a>00148 <span class="preprocessor">#endif </span><span class="comment">/* __CORE_CM4_H_GENERIC */</span>
<a name="l00149"></a>00149 
<a name="l00150"></a>00150 <span class="preprocessor">#ifndef __CMSIS_GENERIC</span>
<a name="l00151"></a>00151 <span class="preprocessor"></span>
<a name="l00152"></a>00152 <span class="preprocessor">#ifndef __CORE_CM4_H_DEPENDANT</span>
<a name="l00153"></a>00153 <span class="preprocessor"></span><span class="preprocessor">#define __CORE_CM4_H_DEPENDANT</span>
<a name="l00154"></a>00154 <span class="preprocessor"></span>
<a name="l00155"></a>00155 <span class="comment">/* check device defines and use defaults */</span>
<a name="l00156"></a>00156 <span class="preprocessor">#if defined __CHECK_DEVICE_DEFINES</span>
<a name="l00157"></a>00157 <span class="preprocessor"></span><span class="preprocessor">  #ifndef __CM4_REV</span>
<a name="l00158"></a>00158 <span class="preprocessor"></span><span class="preprocessor">    #define __CM4_REV               0x0000</span>
<a name="l00159"></a>00159 <span class="preprocessor"></span><span class="preprocessor">    #warning &quot;__CM4_REV not defined in device header file; using default!&quot;</span>
<a name="l00160"></a>00160 <span class="preprocessor"></span><span class="preprocessor">  #endif</span>
<a name="l00161"></a>00161 <span class="preprocessor"></span>
<a name="l00162"></a>00162 <span class="preprocessor">  #ifndef __FPU_PRESENT</span>
<a name="l00163"></a>00163 <span class="preprocessor"></span><span class="preprocessor">    #define __FPU_PRESENT             0</span>
<a name="l00164"></a>00164 <span class="preprocessor"></span><span class="preprocessor">    #warning &quot;__FPU_PRESENT not defined in device header file; using default!&quot;</span>
<a name="l00165"></a>00165 <span class="preprocessor"></span><span class="preprocessor">  #endif</span>
<a name="l00166"></a>00166 <span class="preprocessor"></span>
<a name="l00167"></a>00167 <span class="preprocessor">  #ifndef __MPU_PRESENT</span>
<a name="l00168"></a>00168 <span class="preprocessor"></span><span class="preprocessor">    #define __MPU_PRESENT             0</span>
<a name="l00169"></a>00169 <span class="preprocessor"></span><span class="preprocessor">    #warning &quot;__MPU_PRESENT not defined in device header file; using default!&quot;</span>
<a name="l00170"></a>00170 <span class="preprocessor"></span><span class="preprocessor">  #endif</span>
<a name="l00171"></a>00171 <span class="preprocessor"></span>
<a name="l00172"></a>00172 <span class="preprocessor">  #ifndef __NVIC_PRIO_BITS</span>
<a name="l00173"></a>00173 <span class="preprocessor"></span><span class="preprocessor">    #define __NVIC_PRIO_BITS          4</span>
<a name="l00174"></a>00174 <span class="preprocessor"></span><span class="preprocessor">    #warning &quot;__NVIC_PRIO_BITS not defined in device header file; using default!&quot;</span>
<a name="l00175"></a>00175 <span class="preprocessor"></span><span class="preprocessor">  #endif</span>
<a name="l00176"></a>00176 <span class="preprocessor"></span>
<a name="l00177"></a>00177 <span class="preprocessor">  #ifndef __Vendor_SysTickConfig</span>
<a name="l00178"></a>00178 <span class="preprocessor"></span><span class="preprocessor">    #define __Vendor_SysTickConfig    0</span>
<a name="l00179"></a>00179 <span class="preprocessor"></span><span class="preprocessor">    #warning &quot;__Vendor_SysTickConfig not defined in device header file; using default!&quot;</span>
<a name="l00180"></a>00180 <span class="preprocessor"></span><span class="preprocessor">  #endif</span>
<a name="l00181"></a>00181 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00182"></a>00182 <span class="preprocessor"></span>
<a name="l00183"></a>00183 <span class="comment">/* IO definitions (access restrictions to peripheral registers) */</span>
<a name="l00184"></a>00184 <span class="preprocessor">#ifdef __cplusplus</span>
<a name="l00185"></a>00185 <span class="preprocessor"></span><span class="preprocessor">  #define   __I     volatile             </span>
<a name="l00186"></a>00186 <span class="preprocessor">#else</span>
<a name="l00187"></a>00187 <span class="preprocessor"></span><span class="preprocessor">  #define   __I     volatile const       </span>
<a name="l00188"></a>00188 <span class="preprocessor">#endif</span>
<a name="l00189"></a>00189 <span class="preprocessor"></span><span class="preprocessor">#define     __O     volatile             </span>
<a name="l00190"></a>00190 <span class="preprocessor">#define     __IO    volatile             </span>
<a name="l00192"></a>00192 <span class="preprocessor"></span>
<a name="l00196"></a>00196 <span class="preprocessor"></span><span class="comment">/*******************************************************************************</span>
<a name="l00197"></a>00197 <span class="comment"> *                 Register Abstraction</span>
<a name="l00198"></a>00198 <span class="comment"> ******************************************************************************/</span>
<a name="l00199"></a>00199 
<a name="l00218"></a>00218 <span class="keyword">typedef</span> <span class="keyword">union</span>
<a name="l00219"></a>00219 {
<a name="l00220"></a>00220   <span class="keyword">struct</span>
<a name="l00221"></a>00221   {
<a name="l00222"></a>00222 <span class="preprocessor">#if (__CORTEX_M != 0x04)</span>
<a name="l00223"></a>00223 <span class="preprocessor"></span>    uint32_t _reserved0:27;              
<a name="l00224"></a>00224 <span class="preprocessor">#else</span>
<a name="l00225"></a>00225 <span class="preprocessor"></span>    uint32_t _reserved0:16;              
<a name="l00226"></a>00226     uint32_t GE:4;                       
<a name="l00227"></a>00227     uint32_t _reserved1:7;               
<a name="l00228"></a>00228 <span class="preprocessor">#endif</span>
<a name="l00229"></a>00229 <span class="preprocessor"></span>    uint32_t Q:1;                        
<a name="l00230"></a>00230     uint32_t V:1;                        
<a name="l00231"></a>00231     uint32_t C:1;                        
<a name="l00232"></a>00232     uint32_t Z:1;                        
<a name="l00233"></a>00233     uint32_t N:1;                        
<a name="l00234"></a>00234   } b;                                   
<a name="l00235"></a>00235   uint32_t w;                            
<a name="l00236"></a>00236 } APSR_Type;
<a name="l00237"></a>00237 
<a name="l00238"></a>00238 
<a name="l00241"></a>00241 <span class="keyword">typedef</span> <span class="keyword">union</span>
<a name="l00242"></a>00242 {
<a name="l00243"></a>00243   <span class="keyword">struct</span>
<a name="l00244"></a>00244   {
<a name="l00245"></a>00245     uint32_t ISR:9;                      
<a name="l00246"></a>00246     uint32_t _reserved0:23;              
<a name="l00247"></a>00247   } b;                                   
<a name="l00248"></a>00248   uint32_t w;                            
<a name="l00249"></a>00249 } IPSR_Type;
<a name="l00250"></a>00250 
<a name="l00251"></a>00251 
<a name="l00254"></a>00254 <span class="keyword">typedef</span> <span class="keyword">union</span>
<a name="l00255"></a>00255 {
<a name="l00256"></a>00256   <span class="keyword">struct</span>
<a name="l00257"></a>00257   {
<a name="l00258"></a>00258     uint32_t ISR:9;                      
<a name="l00259"></a>00259 <span class="preprocessor">#if (__CORTEX_M != 0x04)</span>
<a name="l00260"></a>00260 <span class="preprocessor"></span>    uint32_t _reserved0:15;              
<a name="l00261"></a>00261 <span class="preprocessor">#else</span>
<a name="l00262"></a>00262 <span class="preprocessor"></span>    uint32_t _reserved0:7;               
<a name="l00263"></a>00263     uint32_t GE:4;                       
<a name="l00264"></a>00264     uint32_t _reserved1:4;               
<a name="l00265"></a>00265 <span class="preprocessor">#endif</span>
<a name="l00266"></a>00266 <span class="preprocessor"></span>    uint32_t T:1;                        
<a name="l00267"></a>00267     uint32_t IT:2;                       
<a name="l00268"></a>00268     uint32_t Q:1;                        
<a name="l00269"></a>00269     uint32_t V:1;                        
<a name="l00270"></a>00270     uint32_t C:1;                        
<a name="l00271"></a>00271     uint32_t Z:1;                        
<a name="l00272"></a>00272     uint32_t N:1;                        
<a name="l00273"></a>00273   } b;                                   
<a name="l00274"></a>00274   uint32_t w;                            
<a name="l00275"></a>00275 } xPSR_Type;
<a name="l00276"></a>00276 
<a name="l00277"></a>00277 
<a name="l00280"></a>00280 <span class="keyword">typedef</span> <span class="keyword">union</span>
<a name="l00281"></a>00281 {
<a name="l00282"></a>00282   <span class="keyword">struct</span>
<a name="l00283"></a>00283   {
<a name="l00284"></a>00284     uint32_t nPRIV:1;                    
<a name="l00285"></a>00285     uint32_t SPSEL:1;                    
<a name="l00286"></a>00286     uint32_t FPCA:1;                     
<a name="l00287"></a>00287     uint32_t _reserved0:29;              
<a name="l00288"></a>00288   } b;                                   
<a name="l00289"></a>00289   uint32_t w;                            
<a name="l00290"></a>00290 } CONTROL_Type;
<a name="l00291"></a>00291 
<a name="l00303"></a>00303 <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00304"></a>00304 {
<a name="l00305"></a>00305   __IO uint32_t ISER[8];                 
<a name="l00306"></a>00306        uint32_t RESERVED0[24];
<a name="l00307"></a>00307   __IO uint32_t ICER[8];                 
<a name="l00308"></a>00308        uint32_t RSERVED1[24];
<a name="l00309"></a>00309   __IO uint32_t ISPR[8];                 
<a name="l00310"></a>00310        uint32_t RESERVED2[24];
<a name="l00311"></a>00311   __IO uint32_t ICPR[8];                 
<a name="l00312"></a>00312        uint32_t RESERVED3[24];
<a name="l00313"></a>00313   __IO uint32_t IABR[8];                 
<a name="l00314"></a>00314        uint32_t RESERVED4[56];
<a name="l00315"></a>00315   __IO uint8_t  IP[240];                 
<a name="l00316"></a>00316        uint32_t RESERVED5[644];
<a name="l00317"></a>00317   __O  uint32_t STIR;                    
<a name="l00318"></a>00318 }  NVIC_Type;
<a name="l00319"></a>00319 
<a name="l00320"></a>00320 <span class="comment">/* Software Triggered Interrupt Register Definitions */</span>
<a name="l00321"></a>00321 <span class="preprocessor">#define NVIC_STIR_INTID_Pos                 0                                          </span>
<a name="l00322"></a>00322 <span class="preprocessor">#define NVIC_STIR_INTID_Msk                (0x1FFUL &lt;&lt; NVIC_STIR_INTID_Pos)            </span>
<a name="l00324"></a>00324 <span class="preprocessor"></span>
<a name="l00335"></a>00335 <span class="preprocessor">typedef struct</span>
<a name="l00336"></a>00336 <span class="preprocessor"></span>{
<a name="l00337"></a>00337   __I  uint32_t CPUID;                   
<a name="l00338"></a>00338   __IO uint32_t ICSR;                    
<a name="l00339"></a>00339   __IO uint32_t VTOR;                    
<a name="l00340"></a>00340   __IO uint32_t AIRCR;                   
<a name="l00341"></a>00341   __IO uint32_t SCR;                     
<a name="l00342"></a>00342   __IO uint32_t CCR;                     
<a name="l00343"></a>00343   __IO uint8_t  SHP[12];                 
<a name="l00344"></a>00344   __IO uint32_t SHCSR;                   
<a name="l00345"></a>00345   __IO uint32_t CFSR;                    
<a name="l00346"></a>00346   __IO uint32_t HFSR;                    
<a name="l00347"></a>00347   __IO uint32_t DFSR;                    
<a name="l00348"></a>00348   __IO uint32_t MMFAR;                   
<a name="l00349"></a>00349   __IO uint32_t BFAR;                    
<a name="l00350"></a>00350   __IO uint32_t AFSR;                    
<a name="l00351"></a>00351   __I  uint32_t PFR[2];                  
<a name="l00352"></a>00352   __I  uint32_t DFR;                     
<a name="l00353"></a>00353   __I  uint32_t ADR;                     
<a name="l00354"></a>00354   __I  uint32_t MMFR[4];                 
<a name="l00355"></a>00355   __I  uint32_t ISAR[5];                 
<a name="l00356"></a>00356        uint32_t RESERVED0[5];
<a name="l00357"></a>00357   __IO uint32_t CPACR;                   
<a name="l00358"></a>00358 } SCB_Type;
<a name="l00359"></a>00359 
<a name="l00360"></a>00360 <span class="comment">/* SCB CPUID Register Definitions */</span>
<a name="l00361"></a>00361 <span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Pos          24                                             </span>
<a name="l00362"></a>00362 <span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL &lt;&lt; SCB_CPUID_IMPLEMENTER_Pos)          </span>
<a name="l00364"></a>00364 <span class="preprocessor">#define SCB_CPUID_VARIANT_Pos              20                                             </span>
<a name="l00365"></a>00365 <span class="preprocessor">#define SCB_CPUID_VARIANT_Msk              (0xFUL &lt;&lt; SCB_CPUID_VARIANT_Pos)               </span>
<a name="l00367"></a>00367 <span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Pos         16                                             </span>
<a name="l00368"></a>00368 <span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL &lt;&lt; SCB_CPUID_ARCHITECTURE_Pos)          </span>
<a name="l00370"></a>00370 <span class="preprocessor">#define SCB_CPUID_PARTNO_Pos                4                                             </span>
<a name="l00371"></a>00371 <span class="preprocessor">#define SCB_CPUID_PARTNO_Msk               (0xFFFUL &lt;&lt; SCB_CPUID_PARTNO_Pos)              </span>
<a name="l00373"></a>00373 <span class="preprocessor">#define SCB_CPUID_REVISION_Pos              0                                             </span>
<a name="l00374"></a>00374 <span class="preprocessor">#define SCB_CPUID_REVISION_Msk             (0xFUL &lt;&lt; SCB_CPUID_REVISION_Pos)              </span>
<a name="l00376"></a>00376 <span class="preprocessor"></span><span class="comment">/* SCB Interrupt Control State Register Definitions */</span>
<a name="l00377"></a>00377 <span class="preprocessor">#define SCB_ICSR_NMIPENDSET_Pos            31                                             </span>
<a name="l00378"></a>00378 <span class="preprocessor">#define SCB_ICSR_NMIPENDSET_Msk            (1UL &lt;&lt; SCB_ICSR_NMIPENDSET_Pos)               </span>
<a name="l00380"></a>00380 <span class="preprocessor">#define SCB_ICSR_PENDSVSET_Pos             28                                             </span>
<a name="l00381"></a>00381 <span class="preprocessor">#define SCB_ICSR_PENDSVSET_Msk             (1UL &lt;&lt; SCB_ICSR_PENDSVSET_Pos)                </span>
<a name="l00383"></a>00383 <span class="preprocessor">#define SCB_ICSR_PENDSVCLR_Pos             27                                             </span>
<a name="l00384"></a>00384 <span class="preprocessor">#define SCB_ICSR_PENDSVCLR_Msk             (1UL &lt;&lt; SCB_ICSR_PENDSVCLR_Pos)                </span>
<a name="l00386"></a>00386 <span class="preprocessor">#define SCB_ICSR_PENDSTSET_Pos             26                                             </span>
<a name="l00387"></a>00387 <span class="preprocessor">#define SCB_ICSR_PENDSTSET_Msk             (1UL &lt;&lt; SCB_ICSR_PENDSTSET_Pos)                </span>
<a name="l00389"></a>00389 <span class="preprocessor">#define SCB_ICSR_PENDSTCLR_Pos             25                                             </span>
<a name="l00390"></a>00390 <span class="preprocessor">#define SCB_ICSR_PENDSTCLR_Msk             (1UL &lt;&lt; SCB_ICSR_PENDSTCLR_Pos)                </span>
<a name="l00392"></a>00392 <span class="preprocessor">#define SCB_ICSR_ISRPREEMPT_Pos            23                                             </span>
<a name="l00393"></a>00393 <span class="preprocessor">#define SCB_ICSR_ISRPREEMPT_Msk            (1UL &lt;&lt; SCB_ICSR_ISRPREEMPT_Pos)               </span>
<a name="l00395"></a>00395 <span class="preprocessor">#define SCB_ICSR_ISRPENDING_Pos            22                                             </span>
<a name="l00396"></a>00396 <span class="preprocessor">#define SCB_ICSR_ISRPENDING_Msk            (1UL &lt;&lt; SCB_ICSR_ISRPENDING_Pos)               </span>
<a name="l00398"></a>00398 <span class="preprocessor">#define SCB_ICSR_VECTPENDING_Pos           12                                             </span>
<a name="l00399"></a>00399 <span class="preprocessor">#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL &lt;&lt; SCB_ICSR_VECTPENDING_Pos)          </span>
<a name="l00401"></a>00401 <span class="preprocessor">#define SCB_ICSR_RETTOBASE_Pos             11                                             </span>
<a name="l00402"></a>00402 <span class="preprocessor">#define SCB_ICSR_RETTOBASE_Msk             (1UL &lt;&lt; SCB_ICSR_RETTOBASE_Pos)                </span>
<a name="l00404"></a>00404 <span class="preprocessor">#define SCB_ICSR_VECTACTIVE_Pos             0                                             </span>
<a name="l00405"></a>00405 <span class="preprocessor">#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL &lt;&lt; SCB_ICSR_VECTACTIVE_Pos)           </span>
<a name="l00407"></a>00407 <span class="preprocessor"></span><span class="comment">/* SCB Vector Table Offset Register Definitions */</span>
<a name="l00408"></a>00408 <span class="preprocessor">#define SCB_VTOR_TBLOFF_Pos                 7                                             </span>
<a name="l00409"></a>00409 <span class="preprocessor">#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL &lt;&lt; SCB_VTOR_TBLOFF_Pos)           </span>
<a name="l00411"></a>00411 <span class="preprocessor"></span><span class="comment">/* SCB Application Interrupt and Reset Control Register Definitions */</span>
<a name="l00412"></a>00412 <span class="preprocessor">#define SCB_AIRCR_VECTKEY_Pos              16                                             </span>
<a name="l00413"></a>00413 <span class="preprocessor">#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL &lt;&lt; SCB_AIRCR_VECTKEY_Pos)            </span>
<a name="l00415"></a>00415 <span class="preprocessor">#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             </span>
<a name="l00416"></a>00416 <span class="preprocessor">#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL &lt;&lt; SCB_AIRCR_VECTKEYSTAT_Pos)        </span>
<a name="l00418"></a>00418 <span class="preprocessor">#define SCB_AIRCR_ENDIANESS_Pos            15                                             </span>
<a name="l00419"></a>00419 <span class="preprocessor">#define SCB_AIRCR_ENDIANESS_Msk            (1UL &lt;&lt; SCB_AIRCR_ENDIANESS_Pos)               </span>
<a name="l00421"></a>00421 <span class="preprocessor">#define SCB_AIRCR_PRIGROUP_Pos              8                                             </span>
<a name="l00422"></a>00422 <span class="preprocessor">#define SCB_AIRCR_PRIGROUP_Msk             (7UL &lt;&lt; SCB_AIRCR_PRIGROUP_Pos)                </span>
<a name="l00424"></a>00424 <span class="preprocessor">#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             </span>
<a name="l00425"></a>00425 <span class="preprocessor">#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL &lt;&lt; SCB_AIRCR_SYSRESETREQ_Pos)             </span>
<a name="l00427"></a>00427 <span class="preprocessor">#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             </span>
<a name="l00428"></a>00428 <span class="preprocessor">#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL &lt;&lt; SCB_AIRCR_VECTCLRACTIVE_Pos)           </span>
<a name="l00430"></a>00430 <span class="preprocessor">#define SCB_AIRCR_VECTRESET_Pos             0                                             </span>
<a name="l00431"></a>00431 <span class="preprocessor">#define SCB_AIRCR_VECTRESET_Msk            (1UL &lt;&lt; SCB_AIRCR_VECTRESET_Pos)               </span>
<a name="l00433"></a>00433 <span class="preprocessor"></span><span class="comment">/* SCB System Control Register Definitions */</span>
<a name="l00434"></a>00434 <span class="preprocessor">#define SCB_SCR_SEVONPEND_Pos               4                                             </span>
<a name="l00435"></a>00435 <span class="preprocessor">#define SCB_SCR_SEVONPEND_Msk              (1UL &lt;&lt; SCB_SCR_SEVONPEND_Pos)                 </span>
<a name="l00437"></a>00437 <span class="preprocessor">#define SCB_SCR_SLEEPDEEP_Pos               2                                             </span>
<a name="l00438"></a>00438 <span class="preprocessor">#define SCB_SCR_SLEEPDEEP_Msk              (1UL &lt;&lt; SCB_SCR_SLEEPDEEP_Pos)                 </span>
<a name="l00440"></a>00440 <span class="preprocessor">#define SCB_SCR_SLEEPONEXIT_Pos             1                                             </span>
<a name="l00441"></a>00441 <span class="preprocessor">#define SCB_SCR_SLEEPONEXIT_Msk            (1UL &lt;&lt; SCB_SCR_SLEEPONEXIT_Pos)               </span>
<a name="l00443"></a>00443 <span class="preprocessor"></span><span class="comment">/* SCB Configuration Control Register Definitions */</span>
<a name="l00444"></a>00444 <span class="preprocessor">#define SCB_CCR_STKALIGN_Pos                9                                             </span>
<a name="l00445"></a>00445 <span class="preprocessor">#define SCB_CCR_STKALIGN_Msk               (1UL &lt;&lt; SCB_CCR_STKALIGN_Pos)                  </span>
<a name="l00447"></a>00447 <span class="preprocessor">#define SCB_CCR_BFHFNMIGN_Pos               8                                             </span>
<a name="l00448"></a>00448 <span class="preprocessor">#define SCB_CCR_BFHFNMIGN_Msk              (1UL &lt;&lt; SCB_CCR_BFHFNMIGN_Pos)                 </span>
<a name="l00450"></a>00450 <span class="preprocessor">#define SCB_CCR_DIV_0_TRP_Pos               4                                             </span>
<a name="l00451"></a>00451 <span class="preprocessor">#define SCB_CCR_DIV_0_TRP_Msk              (1UL &lt;&lt; SCB_CCR_DIV_0_TRP_Pos)                 </span>
<a name="l00453"></a>00453 <span class="preprocessor">#define SCB_CCR_UNALIGN_TRP_Pos             3                                             </span>
<a name="l00454"></a>00454 <span class="preprocessor">#define SCB_CCR_UNALIGN_TRP_Msk            (1UL &lt;&lt; SCB_CCR_UNALIGN_TRP_Pos)               </span>
<a name="l00456"></a>00456 <span class="preprocessor">#define SCB_CCR_USERSETMPEND_Pos            1                                             </span>
<a name="l00457"></a>00457 <span class="preprocessor">#define SCB_CCR_USERSETMPEND_Msk           (1UL &lt;&lt; SCB_CCR_USERSETMPEND_Pos)              </span>
<a name="l00459"></a>00459 <span class="preprocessor">#define SCB_CCR_NONBASETHRDENA_Pos          0                                             </span>
<a name="l00460"></a>00460 <span class="preprocessor">#define SCB_CCR_NONBASETHRDENA_Msk         (1UL &lt;&lt; SCB_CCR_NONBASETHRDENA_Pos)            </span>
<a name="l00462"></a>00462 <span class="preprocessor"></span><span class="comment">/* SCB System Handler Control and State Register Definitions */</span>
<a name="l00463"></a>00463 <span class="preprocessor">#define SCB_SHCSR_USGFAULTENA_Pos          18                                             </span>
<a name="l00464"></a>00464 <span class="preprocessor">#define SCB_SHCSR_USGFAULTENA_Msk          (1UL &lt;&lt; SCB_SHCSR_USGFAULTENA_Pos)             </span>
<a name="l00466"></a>00466 <span class="preprocessor">#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             </span>
<a name="l00467"></a>00467 <span class="preprocessor">#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL &lt;&lt; SCB_SHCSR_BUSFAULTENA_Pos)             </span>
<a name="l00469"></a>00469 <span class="preprocessor">#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             </span>
<a name="l00470"></a>00470 <span class="preprocessor">#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL &lt;&lt; SCB_SHCSR_MEMFAULTENA_Pos)             </span>
<a name="l00472"></a>00472 <span class="preprocessor">#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             </span>
<a name="l00473"></a>00473 <span class="preprocessor">#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL &lt;&lt; SCB_SHCSR_SVCALLPENDED_Pos)            </span>
<a name="l00475"></a>00475 <span class="preprocessor">#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             </span>
<a name="l00476"></a>00476 <span class="preprocessor">#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL &lt;&lt; SCB_SHCSR_BUSFAULTPENDED_Pos)          </span>
<a name="l00478"></a>00478 <span class="preprocessor">#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             </span>
<a name="l00479"></a>00479 <span class="preprocessor">#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL &lt;&lt; SCB_SHCSR_MEMFAULTPENDED_Pos)          </span>
<a name="l00481"></a>00481 <span class="preprocessor">#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             </span>
<a name="l00482"></a>00482 <span class="preprocessor">#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL &lt;&lt; SCB_SHCSR_USGFAULTPENDED_Pos)          </span>
<a name="l00484"></a>00484 <span class="preprocessor">#define SCB_SHCSR_SYSTICKACT_Pos           11                                             </span>
<a name="l00485"></a>00485 <span class="preprocessor">#define SCB_SHCSR_SYSTICKACT_Msk           (1UL &lt;&lt; SCB_SHCSR_SYSTICKACT_Pos)              </span>
<a name="l00487"></a>00487 <span class="preprocessor">#define SCB_SHCSR_PENDSVACT_Pos            10                                             </span>
<a name="l00488"></a>00488 <span class="preprocessor">#define SCB_SHCSR_PENDSVACT_Msk            (1UL &lt;&lt; SCB_SHCSR_PENDSVACT_Pos)               </span>
<a name="l00490"></a>00490 <span class="preprocessor">#define SCB_SHCSR_MONITORACT_Pos            8                                             </span>
<a name="l00491"></a>00491 <span class="preprocessor">#define SCB_SHCSR_MONITORACT_Msk           (1UL &lt;&lt; SCB_SHCSR_MONITORACT_Pos)              </span>
<a name="l00493"></a>00493 <span class="preprocessor">#define SCB_SHCSR_SVCALLACT_Pos             7                                             </span>
<a name="l00494"></a>00494 <span class="preprocessor">#define SCB_SHCSR_SVCALLACT_Msk            (1UL &lt;&lt; SCB_SHCSR_SVCALLACT_Pos)               </span>
<a name="l00496"></a>00496 <span class="preprocessor">#define SCB_SHCSR_USGFAULTACT_Pos           3                                             </span>
<a name="l00497"></a>00497 <span class="preprocessor">#define SCB_SHCSR_USGFAULTACT_Msk          (1UL &lt;&lt; SCB_SHCSR_USGFAULTACT_Pos)             </span>
<a name="l00499"></a>00499 <span class="preprocessor">#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             </span>
<a name="l00500"></a>00500 <span class="preprocessor">#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL &lt;&lt; SCB_SHCSR_BUSFAULTACT_Pos)             </span>
<a name="l00502"></a>00502 <span class="preprocessor">#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             </span>
<a name="l00503"></a>00503 <span class="preprocessor">#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL &lt;&lt; SCB_SHCSR_MEMFAULTACT_Pos)             </span>
<a name="l00505"></a>00505 <span class="preprocessor"></span><span class="comment">/* SCB Configurable Fault Status Registers Definitions */</span>
<a name="l00506"></a>00506 <span class="preprocessor">#define SCB_CFSR_USGFAULTSR_Pos            16                                             </span>
<a name="l00507"></a>00507 <span class="preprocessor">#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL &lt;&lt; SCB_CFSR_USGFAULTSR_Pos)          </span>
<a name="l00509"></a>00509 <span class="preprocessor">#define SCB_CFSR_BUSFAULTSR_Pos             8                                             </span>
<a name="l00510"></a>00510 <span class="preprocessor">#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL &lt;&lt; SCB_CFSR_BUSFAULTSR_Pos)            </span>
<a name="l00512"></a>00512 <span class="preprocessor">#define SCB_CFSR_MEMFAULTSR_Pos             0                                             </span>
<a name="l00513"></a>00513 <span class="preprocessor">#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL &lt;&lt; SCB_CFSR_MEMFAULTSR_Pos)            </span>
<a name="l00515"></a>00515 <span class="preprocessor"></span><span class="comment">/* SCB Hard Fault Status Registers Definitions */</span>
<a name="l00516"></a>00516 <span class="preprocessor">#define SCB_HFSR_DEBUGEVT_Pos              31                                             </span>
<a name="l00517"></a>00517 <span class="preprocessor">#define SCB_HFSR_DEBUGEVT_Msk              (1UL &lt;&lt; SCB_HFSR_DEBUGEVT_Pos)                 </span>
<a name="l00519"></a>00519 <span class="preprocessor">#define SCB_HFSR_FORCED_Pos                30                                             </span>
<a name="l00520"></a>00520 <span class="preprocessor">#define SCB_HFSR_FORCED_Msk                (1UL &lt;&lt; SCB_HFSR_FORCED_Pos)                   </span>
<a name="l00522"></a>00522 <span class="preprocessor">#define SCB_HFSR_VECTTBL_Pos                1                                             </span>
<a name="l00523"></a>00523 <span class="preprocessor">#define SCB_HFSR_VECTTBL_Msk               (1UL &lt;&lt; SCB_HFSR_VECTTBL_Pos)                  </span>
<a name="l00525"></a>00525 <span class="preprocessor"></span><span class="comment">/* SCB Debug Fault Status Register Definitions */</span>
<a name="l00526"></a>00526 <span class="preprocessor">#define SCB_DFSR_EXTERNAL_Pos               4                                             </span>
<a name="l00527"></a>00527 <span class="preprocessor">#define SCB_DFSR_EXTERNAL_Msk              (1UL &lt;&lt; SCB_DFSR_EXTERNAL_Pos)                 </span>
<a name="l00529"></a>00529 <span class="preprocessor">#define SCB_DFSR_VCATCH_Pos                 3                                             </span>
<a name="l00530"></a>00530 <span class="preprocessor">#define SCB_DFSR_VCATCH_Msk                (1UL &lt;&lt; SCB_DFSR_VCATCH_Pos)                   </span>
<a name="l00532"></a>00532 <span class="preprocessor">#define SCB_DFSR_DWTTRAP_Pos                2                                             </span>
<a name="l00533"></a>00533 <span class="preprocessor">#define SCB_DFSR_DWTTRAP_Msk               (1UL &lt;&lt; SCB_DFSR_DWTTRAP_Pos)                  </span>
<a name="l00535"></a>00535 <span class="preprocessor">#define SCB_DFSR_BKPT_Pos                   1                                             </span>
<a name="l00536"></a>00536 <span class="preprocessor">#define SCB_DFSR_BKPT_Msk                  (1UL &lt;&lt; SCB_DFSR_BKPT_Pos)                     </span>
<a name="l00538"></a>00538 <span class="preprocessor">#define SCB_DFSR_HALTED_Pos                 0                                             </span>
<a name="l00539"></a>00539 <span class="preprocessor">#define SCB_DFSR_HALTED_Msk                (1UL &lt;&lt; SCB_DFSR_HALTED_Pos)                   </span>
<a name="l00541"></a>00541 <span class="preprocessor"></span>
<a name="l00552"></a>00552 <span class="preprocessor">typedef struct</span>
<a name="l00553"></a>00553 <span class="preprocessor"></span>{
<a name="l00554"></a>00554        uint32_t RESERVED0[1];
<a name="l00555"></a>00555   __I  uint32_t ICTR;                    
<a name="l00556"></a>00556   __IO uint32_t ACTLR;                   
<a name="l00557"></a>00557 } SCnSCB_Type;
<a name="l00558"></a>00558 
<a name="l00559"></a>00559 <span class="comment">/* Interrupt Controller Type Register Definitions */</span>
<a name="l00560"></a>00560 <span class="preprocessor">#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          </span>
<a name="l00561"></a>00561 <span class="preprocessor">#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL &lt;&lt; SCnSCB_ICTR_INTLINESNUM_Pos)      </span>
<a name="l00563"></a>00563 <span class="preprocessor"></span><span class="comment">/* Auxiliary Control Register Definitions */</span>
<a name="l00564"></a>00564 <span class="preprocessor">#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          </span>
<a name="l00565"></a>00565 <span class="preprocessor">#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL &lt;&lt; SCnSCB_ACTLR_DISOOFP_Pos)           </span>
<a name="l00567"></a>00567 <span class="preprocessor">#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          </span>
<a name="l00568"></a>00568 <span class="preprocessor">#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL &lt;&lt; SCnSCB_ACTLR_DISFPCA_Pos)           </span>
<a name="l00570"></a>00570 <span class="preprocessor">#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          </span>
<a name="l00571"></a>00571 <span class="preprocessor">#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL &lt;&lt; SCnSCB_ACTLR_DISFOLD_Pos)           </span>
<a name="l00573"></a>00573 <span class="preprocessor">#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          </span>
<a name="l00574"></a>00574 <span class="preprocessor">#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL &lt;&lt; SCnSCB_ACTLR_DISDEFWBUF_Pos)        </span>
<a name="l00576"></a>00576 <span class="preprocessor">#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          </span>
<a name="l00577"></a>00577 <span class="preprocessor">#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL &lt;&lt; SCnSCB_ACTLR_DISMCYCINT_Pos)        </span>
<a name="l00579"></a>00579 <span class="preprocessor"></span>
<a name="l00590"></a>00590 <span class="preprocessor">typedef struct</span>
<a name="l00591"></a>00591 <span class="preprocessor"></span>{
<a name="l00592"></a>00592   __IO uint32_t CTRL;                    
<a name="l00593"></a>00593   __IO uint32_t LOAD;                    
<a name="l00594"></a>00594   __IO uint32_t VAL;                     
<a name="l00595"></a>00595   __I  uint32_t CALIB;                   
<a name="l00596"></a>00596 } SysTick_Type;
<a name="l00597"></a>00597 
<a name="l00598"></a>00598 <span class="comment">/* SysTick Control / Status Register Definitions */</span>
<a name="l00599"></a>00599 <span class="preprocessor">#define SysTick_CTRL_COUNTFLAG_Pos         16                                             </span>
<a name="l00600"></a>00600 <span class="preprocessor">#define SysTick_CTRL_COUNTFLAG_Msk         (1UL &lt;&lt; SysTick_CTRL_COUNTFLAG_Pos)            </span>
<a name="l00602"></a>00602 <span class="preprocessor">#define SysTick_CTRL_CLKSOURCE_Pos          2                                             </span>
<a name="l00603"></a>00603 <span class="preprocessor">#define SysTick_CTRL_CLKSOURCE_Msk         (1UL &lt;&lt; SysTick_CTRL_CLKSOURCE_Pos)            </span>
<a name="l00605"></a>00605 <span class="preprocessor">#define SysTick_CTRL_TICKINT_Pos            1                                             </span>
<a name="l00606"></a>00606 <span class="preprocessor">#define SysTick_CTRL_TICKINT_Msk           (1UL &lt;&lt; SysTick_CTRL_TICKINT_Pos)              </span>
<a name="l00608"></a>00608 <span class="preprocessor">#define SysTick_CTRL_ENABLE_Pos             0                                             </span>
<a name="l00609"></a>00609 <span class="preprocessor">#define SysTick_CTRL_ENABLE_Msk            (1UL &lt;&lt; SysTick_CTRL_ENABLE_Pos)               </span>
<a name="l00611"></a>00611 <span class="preprocessor"></span><span class="comment">/* SysTick Reload Register Definitions */</span>
<a name="l00612"></a>00612 <span class="preprocessor">#define SysTick_LOAD_RELOAD_Pos             0                                             </span>
<a name="l00613"></a>00613 <span class="preprocessor">#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL &lt;&lt; SysTick_LOAD_RELOAD_Pos)        </span>
<a name="l00615"></a>00615 <span class="preprocessor"></span><span class="comment">/* SysTick Current Register Definitions */</span>
<a name="l00616"></a>00616 <span class="preprocessor">#define SysTick_VAL_CURRENT_Pos             0                                             </span>
<a name="l00617"></a>00617 <span class="preprocessor">#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL &lt;&lt; SysTick_VAL_CURRENT_Pos)        </span>
<a name="l00619"></a>00619 <span class="preprocessor"></span><span class="comment">/* SysTick Calibration Register Definitions */</span>
<a name="l00620"></a>00620 <span class="preprocessor">#define SysTick_CALIB_NOREF_Pos            31                                             </span>
<a name="l00621"></a>00621 <span class="preprocessor">#define SysTick_CALIB_NOREF_Msk            (1UL &lt;&lt; SysTick_CALIB_NOREF_Pos)               </span>
<a name="l00623"></a>00623 <span class="preprocessor">#define SysTick_CALIB_SKEW_Pos             30                                             </span>
<a name="l00624"></a>00624 <span class="preprocessor">#define SysTick_CALIB_SKEW_Msk             (1UL &lt;&lt; SysTick_CALIB_SKEW_Pos)                </span>
<a name="l00626"></a>00626 <span class="preprocessor">#define SysTick_CALIB_TENMS_Pos             0                                             </span>
<a name="l00627"></a>00627 <span class="preprocessor">#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL &lt;&lt; SysTick_VAL_CURRENT_Pos)        </span>
<a name="l00629"></a>00629 <span class="preprocessor"></span>
<a name="l00640"></a>00640 <span class="preprocessor">typedef struct</span>
<a name="l00641"></a>00641 <span class="preprocessor"></span>{
<a name="l00642"></a>00642   __O  <span class="keyword">union</span>
<a name="l00643"></a>00643   {
<a name="l00644"></a>00644     __O  uint8_t    u8;                  
<a name="l00645"></a>00645     __O  uint16_t   u16;                 
<a name="l00646"></a>00646     __O  uint32_t   u32;                 
<a name="l00647"></a>00647   }  PORT [32];                          
<a name="l00648"></a>00648        uint32_t RESERVED0[864];
<a name="l00649"></a>00649   __IO uint32_t TER;                     
<a name="l00650"></a>00650        uint32_t RESERVED1[15];
<a name="l00651"></a>00651   __IO uint32_t TPR;                     
<a name="l00652"></a>00652        uint32_t RESERVED2[15];
<a name="l00653"></a>00653   __IO uint32_t TCR;                     
<a name="l00654"></a>00654 } ITM_Type;
<a name="l00655"></a>00655 
<a name="l00656"></a>00656 <span class="comment">/* ITM Trace Privilege Register Definitions */</span>
<a name="l00657"></a>00657 <span class="preprocessor">#define ITM_TPR_PRIVMASK_Pos                0                                          </span>
<a name="l00658"></a>00658 <span class="preprocessor">#define ITM_TPR_PRIVMASK_Msk               (0xFUL &lt;&lt; ITM_TPR_PRIVMASK_Pos)             </span>
<a name="l00660"></a>00660 <span class="preprocessor"></span><span class="comment">/* ITM Trace Control Register Definitions */</span>
<a name="l00661"></a>00661 <span class="preprocessor">#define ITM_TCR_BUSY_Pos                   23                                          </span>
<a name="l00662"></a>00662 <span class="preprocessor">#define ITM_TCR_BUSY_Msk                   (1UL &lt;&lt; ITM_TCR_BUSY_Pos)                   </span>
<a name="l00664"></a>00664 <span class="preprocessor">#define ITM_TCR_TraceBusID_Pos             16                                          </span>
<a name="l00665"></a>00665 <span class="preprocessor">#define ITM_TCR_TraceBusID_Msk             (0x7FUL &lt;&lt; ITM_TCR_TraceBusID_Pos)          </span>
<a name="l00667"></a>00667 <span class="preprocessor">#define ITM_TCR_GTSFREQ_Pos                10                                          </span>
<a name="l00668"></a>00668 <span class="preprocessor">#define ITM_TCR_GTSFREQ_Msk                (3UL &lt;&lt; ITM_TCR_GTSFREQ_Pos)                </span>
<a name="l00670"></a>00670 <span class="preprocessor">#define ITM_TCR_TSPrescale_Pos              8                                          </span>
<a name="l00671"></a>00671 <span class="preprocessor">#define ITM_TCR_TSPrescale_Msk             (3UL &lt;&lt; ITM_TCR_TSPrescale_Pos)             </span>
<a name="l00673"></a>00673 <span class="preprocessor">#define ITM_TCR_SWOENA_Pos                  4                                          </span>
<a name="l00674"></a>00674 <span class="preprocessor">#define ITM_TCR_SWOENA_Msk                 (1UL &lt;&lt; ITM_TCR_SWOENA_Pos)                 </span>
<a name="l00676"></a>00676 <span class="preprocessor">#define ITM_TCR_TXENA_Pos                   3                                          </span>
<a name="l00677"></a>00677 <span class="preprocessor">#define ITM_TCR_TXENA_Msk                  (1UL &lt;&lt; ITM_TCR_TXENA_Pos)                  </span>
<a name="l00679"></a>00679 <span class="preprocessor">#define ITM_TCR_SYNCENA_Pos                 2                                          </span>
<a name="l00680"></a>00680 <span class="preprocessor">#define ITM_TCR_SYNCENA_Msk                (1UL &lt;&lt; ITM_TCR_SYNCENA_Pos)                </span>
<a name="l00682"></a>00682 <span class="preprocessor">#define ITM_TCR_TSENA_Pos                   1                                          </span>
<a name="l00683"></a>00683 <span class="preprocessor">#define ITM_TCR_TSENA_Msk                  (1UL &lt;&lt; ITM_TCR_TSENA_Pos)                  </span>
<a name="l00685"></a>00685 <span class="preprocessor">#define ITM_TCR_ITMENA_Pos                  0                                          </span>
<a name="l00686"></a>00686 <span class="preprocessor">#define ITM_TCR_ITMENA_Msk                 (1UL &lt;&lt; ITM_TCR_ITMENA_Pos)                 </span>
<a name="l00688"></a>00688 <span class="preprocessor"> </span><span class="comment">/* end of group CMSIS_ITM */</span>
<a name="l00689"></a>00689 
<a name="l00690"></a>00690 
<a name="l00691"></a>00691 <span class="preprocessor">#if (__MPU_PRESENT == 1)</span>
<a name="l00692"></a>00692 <span class="preprocessor"></span>
<a name="l00700"></a>00700 <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00701"></a>00701 {
<a name="l00702"></a>00702   __I  uint32_t TYPE;                    
<a name="l00703"></a>00703   __IO uint32_t CTRL;                    
<a name="l00704"></a>00704   __IO uint32_t RNR;                     
<a name="l00705"></a>00705   __IO uint32_t RBAR;                    
<a name="l00706"></a>00706   __IO uint32_t RASR;                    
<a name="l00707"></a>00707   __IO uint32_t RBAR_A1;                 
<a name="l00708"></a>00708   __IO uint32_t RASR_A1;                 
<a name="l00709"></a>00709   __IO uint32_t RBAR_A2;                 
<a name="l00710"></a>00710   __IO uint32_t RASR_A2;                 
<a name="l00711"></a>00711   __IO uint32_t RBAR_A3;                 
<a name="l00712"></a>00712   __IO uint32_t RASR_A3;                 
<a name="l00713"></a>00713 } MPU_Type;
<a name="l00714"></a>00714 
<a name="l00715"></a>00715 <span class="comment">/* MPU Type Register */</span>
<a name="l00716"></a>00716 <span class="preprocessor">#define MPU_TYPE_IREGION_Pos               16                                             </span>
<a name="l00717"></a>00717 <span class="preprocessor">#define MPU_TYPE_IREGION_Msk               (0xFFUL &lt;&lt; MPU_TYPE_IREGION_Pos)               </span>
<a name="l00719"></a>00719 <span class="preprocessor">#define MPU_TYPE_DREGION_Pos                8                                             </span>
<a name="l00720"></a>00720 <span class="preprocessor">#define MPU_TYPE_DREGION_Msk               (0xFFUL &lt;&lt; MPU_TYPE_DREGION_Pos)               </span>
<a name="l00722"></a>00722 <span class="preprocessor">#define MPU_TYPE_SEPARATE_Pos               0                                             </span>
<a name="l00723"></a>00723 <span class="preprocessor">#define MPU_TYPE_SEPARATE_Msk              (1UL &lt;&lt; MPU_TYPE_SEPARATE_Pos)                 </span>
<a name="l00725"></a>00725 <span class="preprocessor"></span><span class="comment">/* MPU Control Register */</span>
<a name="l00726"></a>00726 <span class="preprocessor">#define MPU_CTRL_PRIVDEFENA_Pos             2                                             </span>
<a name="l00727"></a>00727 <span class="preprocessor">#define MPU_CTRL_PRIVDEFENA_Msk            (1UL &lt;&lt; MPU_CTRL_PRIVDEFENA_Pos)               </span>
<a name="l00729"></a>00729 <span class="preprocessor">#define MPU_CTRL_HFNMIENA_Pos               1                                             </span>
<a name="l00730"></a>00730 <span class="preprocessor">#define MPU_CTRL_HFNMIENA_Msk              (1UL &lt;&lt; MPU_CTRL_HFNMIENA_Pos)                 </span>
<a name="l00732"></a>00732 <span class="preprocessor">#define MPU_CTRL_ENABLE_Pos                 0                                             </span>
<a name="l00733"></a>00733 <span class="preprocessor">#define MPU_CTRL_ENABLE_Msk                (1UL &lt;&lt; MPU_CTRL_ENABLE_Pos)                   </span>
<a name="l00735"></a>00735 <span class="preprocessor"></span><span class="comment">/* MPU Region Number Register */</span>
<a name="l00736"></a>00736 <span class="preprocessor">#define MPU_RNR_REGION_Pos                  0                                             </span>
<a name="l00737"></a>00737 <span class="preprocessor">#define MPU_RNR_REGION_Msk                 (0xFFUL &lt;&lt; MPU_RNR_REGION_Pos)                 </span>
<a name="l00739"></a>00739 <span class="preprocessor"></span><span class="comment">/* MPU Region Base Address Register */</span>
<a name="l00740"></a>00740 <span class="preprocessor">#define MPU_RBAR_ADDR_Pos                   5                                             </span>
<a name="l00741"></a>00741 <span class="preprocessor">#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL &lt;&lt; MPU_RBAR_ADDR_Pos)             </span>
<a name="l00743"></a>00743 <span class="preprocessor">#define MPU_RBAR_VALID_Pos                  4                                             </span>
<a name="l00744"></a>00744 <span class="preprocessor">#define MPU_RBAR_VALID_Msk                 (1UL &lt;&lt; MPU_RBAR_VALID_Pos)                    </span>
<a name="l00746"></a>00746 <span class="preprocessor">#define MPU_RBAR_REGION_Pos                 0                                             </span>
<a name="l00747"></a>00747 <span class="preprocessor">#define MPU_RBAR_REGION_Msk                (0xFUL &lt;&lt; MPU_RBAR_REGION_Pos)                 </span>
<a name="l00749"></a>00749 <span class="preprocessor"></span><span class="comment">/* MPU Region Attribute and Size Register */</span>
<a name="l00750"></a>00750 <span class="preprocessor">#define MPU_RASR_ATTRS_Pos                 16                                             </span>
<a name="l00751"></a>00751 <span class="preprocessor">#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL &lt;&lt; MPU_RASR_ATTRS_Pos)               </span>
<a name="l00753"></a>00753 <span class="preprocessor">#define MPU_RASR_SRD_Pos                    8                                             </span>
<a name="l00754"></a>00754 <span class="preprocessor">#define MPU_RASR_SRD_Msk                   (0xFFUL &lt;&lt; MPU_RASR_SRD_Pos)                   </span>
<a name="l00756"></a>00756 <span class="preprocessor">#define MPU_RASR_SIZE_Pos                   1                                             </span>
<a name="l00757"></a>00757 <span class="preprocessor">#define MPU_RASR_SIZE_Msk                  (0x1FUL &lt;&lt; MPU_RASR_SIZE_Pos)                  </span>
<a name="l00759"></a>00759 <span class="preprocessor">#define MPU_RASR_ENABLE_Pos                 0                                             </span>
<a name="l00760"></a>00760 <span class="preprocessor">#define MPU_RASR_ENABLE_Msk                (1UL &lt;&lt; MPU_RASR_ENABLE_Pos)                   </span>
<a name="l00762"></a>00762 <span class="preprocessor"></span>
<a name="l00763"></a>00763 <span class="preprocessor">#endif</span>
<a name="l00764"></a>00764 <span class="preprocessor"></span>
<a name="l00765"></a>00765 
<a name="l00766"></a>00766 <span class="preprocessor">#if (__FPU_PRESENT == 1)</span>
<a name="l00767"></a>00767 <span class="preprocessor"></span>
<a name="l00775"></a>00775 <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00776"></a>00776 {
<a name="l00777"></a>00777        uint32_t RESERVED0[1];
<a name="l00778"></a>00778   __IO uint32_t FPCCR;                   
<a name="l00779"></a>00779   __IO uint32_t FPCAR;                   
<a name="l00780"></a>00780   __IO uint32_t FPDSCR;                  
<a name="l00781"></a>00781   __I  uint32_t MVFR0;                   
<a name="l00782"></a>00782   __I  uint32_t MVFR1;                   
<a name="l00783"></a>00783 } FPU_Type;
<a name="l00784"></a>00784 
<a name="l00785"></a>00785 <span class="comment">/* Floating-Point Context Control Register */</span>
<a name="l00786"></a>00786 <span class="preprocessor">#define FPU_FPCCR_ASPEN_Pos                31                                             </span>
<a name="l00787"></a>00787 <span class="preprocessor">#define FPU_FPCCR_ASPEN_Msk                (1UL &lt;&lt; FPU_FPCCR_ASPEN_Pos)                   </span>
<a name="l00789"></a>00789 <span class="preprocessor">#define FPU_FPCCR_LSPEN_Pos                30                                             </span>
<a name="l00790"></a>00790 <span class="preprocessor">#define FPU_FPCCR_LSPEN_Msk                (1UL &lt;&lt; FPU_FPCCR_LSPEN_Pos)                   </span>
<a name="l00792"></a>00792 <span class="preprocessor">#define FPU_FPCCR_MONRDY_Pos                8                                             </span>
<a name="l00793"></a>00793 <span class="preprocessor">#define FPU_FPCCR_MONRDY_Msk               (1UL &lt;&lt; FPU_FPCCR_MONRDY_Pos)                  </span>
<a name="l00795"></a>00795 <span class="preprocessor">#define FPU_FPCCR_BFRDY_Pos                 6                                             </span>
<a name="l00796"></a>00796 <span class="preprocessor">#define FPU_FPCCR_BFRDY_Msk                (1UL &lt;&lt; FPU_FPCCR_BFRDY_Pos)                   </span>
<a name="l00798"></a>00798 <span class="preprocessor">#define FPU_FPCCR_MMRDY_Pos                 5                                             </span>
<a name="l00799"></a>00799 <span class="preprocessor">#define FPU_FPCCR_MMRDY_Msk                (1UL &lt;&lt; FPU_FPCCR_MMRDY_Pos)                   </span>
<a name="l00801"></a>00801 <span class="preprocessor">#define FPU_FPCCR_HFRDY_Pos                 4                                             </span>
<a name="l00802"></a>00802 <span class="preprocessor">#define FPU_FPCCR_HFRDY_Msk                (1UL &lt;&lt; FPU_FPCCR_HFRDY_Pos)                   </span>
<a name="l00804"></a>00804 <span class="preprocessor">#define FPU_FPCCR_THREAD_Pos                3                                             </span>
<a name="l00805"></a>00805 <span class="preprocessor">#define FPU_FPCCR_THREAD_Msk               (1UL &lt;&lt; FPU_FPCCR_THREAD_Pos)                  </span>
<a name="l00807"></a>00807 <span class="preprocessor">#define FPU_FPCCR_USER_Pos                  1                                             </span>
<a name="l00808"></a>00808 <span class="preprocessor">#define FPU_FPCCR_USER_Msk                 (1UL &lt;&lt; FPU_FPCCR_USER_Pos)                    </span>
<a name="l00810"></a>00810 <span class="preprocessor">#define FPU_FPCCR_LSPACT_Pos                0                                             </span>
<a name="l00811"></a>00811 <span class="preprocessor">#define FPU_FPCCR_LSPACT_Msk               (1UL &lt;&lt; FPU_FPCCR_LSPACT_Pos)                  </span>
<a name="l00813"></a>00813 <span class="preprocessor"></span><span class="comment">/* Floating-Point Context Address Register */</span>
<a name="l00814"></a>00814 <span class="preprocessor">#define FPU_FPCAR_ADDRESS_Pos               3                                             </span>
<a name="l00815"></a>00815 <span class="preprocessor">#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL &lt;&lt; FPU_FPCAR_ADDRESS_Pos)        </span>
<a name="l00817"></a>00817 <span class="preprocessor"></span><span class="comment">/* Floating-Point Default Status Control Register */</span>
<a name="l00818"></a>00818 <span class="preprocessor">#define FPU_FPDSCR_AHP_Pos                 26                                             </span>
<a name="l00819"></a>00819 <span class="preprocessor">#define FPU_FPDSCR_AHP_Msk                 (1UL &lt;&lt; FPU_FPDSCR_AHP_Pos)                    </span>
<a name="l00821"></a>00821 <span class="preprocessor">#define FPU_FPDSCR_DN_Pos                  25                                             </span>
<a name="l00822"></a>00822 <span class="preprocessor">#define FPU_FPDSCR_DN_Msk                  (1UL &lt;&lt; FPU_FPDSCR_DN_Pos)                     </span>
<a name="l00824"></a>00824 <span class="preprocessor">#define FPU_FPDSCR_FZ_Pos                  24                                             </span>
<a name="l00825"></a>00825 <span class="preprocessor">#define FPU_FPDSCR_FZ_Msk                  (1UL &lt;&lt; FPU_FPDSCR_FZ_Pos)                     </span>
<a name="l00827"></a>00827 <span class="preprocessor">#define FPU_FPDSCR_RMode_Pos               22                                             </span>
<a name="l00828"></a>00828 <span class="preprocessor">#define FPU_FPDSCR_RMode_Msk               (3UL &lt;&lt; FPU_FPDSCR_RMode_Pos)                  </span>
<a name="l00830"></a>00830 <span class="preprocessor"></span><span class="comment">/* Media and FP Feature Register 0 */</span>
<a name="l00831"></a>00831 <span class="preprocessor">#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             </span>
<a name="l00832"></a>00832 <span class="preprocessor">#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL &lt;&lt; FPU_MVFR0_FP_rounding_modes_Pos)     </span>
<a name="l00834"></a>00834 <span class="preprocessor">#define FPU_MVFR0_Short_vectors_Pos        24                                             </span>
<a name="l00835"></a>00835 <span class="preprocessor">#define FPU_MVFR0_Short_vectors_Msk        (0xFUL &lt;&lt; FPU_MVFR0_Short_vectors_Pos)         </span>
<a name="l00837"></a>00837 <span class="preprocessor">#define FPU_MVFR0_Square_root_Pos          20                                             </span>
<a name="l00838"></a>00838 <span class="preprocessor">#define FPU_MVFR0_Square_root_Msk          (0xFUL &lt;&lt; FPU_MVFR0_Square_root_Pos)           </span>
<a name="l00840"></a>00840 <span class="preprocessor">#define FPU_MVFR0_Divide_Pos               16                                             </span>
<a name="l00841"></a>00841 <span class="preprocessor">#define FPU_MVFR0_Divide_Msk               (0xFUL &lt;&lt; FPU_MVFR0_Divide_Pos)                </span>
<a name="l00843"></a>00843 <span class="preprocessor">#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             </span>
<a name="l00844"></a>00844 <span class="preprocessor">#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL &lt;&lt; FPU_MVFR0_FP_excep_trapping_Pos)     </span>
<a name="l00846"></a>00846 <span class="preprocessor">#define FPU_MVFR0_Double_precision_Pos      8                                             </span>
<a name="l00847"></a>00847 <span class="preprocessor">#define FPU_MVFR0_Double_precision_Msk     (0xFUL &lt;&lt; FPU_MVFR0_Double_precision_Pos)      </span>
<a name="l00849"></a>00849 <span class="preprocessor">#define FPU_MVFR0_Single_precision_Pos      4                                             </span>
<a name="l00850"></a>00850 <span class="preprocessor">#define FPU_MVFR0_Single_precision_Msk     (0xFUL &lt;&lt; FPU_MVFR0_Single_precision_Pos)      </span>
<a name="l00852"></a>00852 <span class="preprocessor">#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             </span>
<a name="l00853"></a>00853 <span class="preprocessor">#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL &lt;&lt; FPU_MVFR0_A_SIMD_registers_Pos)      </span>
<a name="l00855"></a>00855 <span class="preprocessor"></span><span class="comment">/* Media and FP Feature Register 1 */</span>
<a name="l00856"></a>00856 <span class="preprocessor">#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             </span>
<a name="l00857"></a>00857 <span class="preprocessor">#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL &lt;&lt; FPU_MVFR1_FP_fused_MAC_Pos)          </span>
<a name="l00859"></a>00859 <span class="preprocessor">#define FPU_MVFR1_FP_HPFP_Pos              24                                             </span>
<a name="l00860"></a>00860 <span class="preprocessor">#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL &lt;&lt; FPU_MVFR1_FP_HPFP_Pos)               </span>
<a name="l00862"></a>00862 <span class="preprocessor">#define FPU_MVFR1_D_NaN_mode_Pos            4                                             </span>
<a name="l00863"></a>00863 <span class="preprocessor">#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL &lt;&lt; FPU_MVFR1_D_NaN_mode_Pos)            </span>
<a name="l00865"></a>00865 <span class="preprocessor">#define FPU_MVFR1_FtZ_mode_Pos              0                                             </span>
<a name="l00866"></a>00866 <span class="preprocessor">#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL &lt;&lt; FPU_MVFR1_FtZ_mode_Pos)              </span>
<a name="l00868"></a>00868 <span class="preprocessor"></span>
<a name="l00869"></a>00869 <span class="preprocessor">#endif</span>
<a name="l00870"></a>00870 <span class="preprocessor"></span>
<a name="l00871"></a>00871 
<a name="l00880"></a>00880 <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00881"></a>00881 {
<a name="l00882"></a>00882   __IO uint32_t DHCSR;                   
<a name="l00883"></a>00883   __O  uint32_t DCRSR;                   
<a name="l00884"></a>00884   __IO uint32_t DCRDR;                   
<a name="l00885"></a>00885   __IO uint32_t DEMCR;                   
<a name="l00886"></a>00886 } CoreDebug_Type;
<a name="l00887"></a>00887 
<a name="l00888"></a>00888 <span class="comment">/* Debug Halting Control and Status Register */</span>
<a name="l00889"></a>00889 <span class="preprocessor">#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             </span>
<a name="l00890"></a>00890 <span class="preprocessor">#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL &lt;&lt; CoreDebug_DHCSR_DBGKEY_Pos)       </span>
<a name="l00892"></a>00892 <span class="preprocessor">#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             </span>
<a name="l00893"></a>00893 <span class="preprocessor">#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL &lt;&lt; CoreDebug_DHCSR_S_RESET_ST_Pos)        </span>
<a name="l00895"></a>00895 <span class="preprocessor">#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             </span>
<a name="l00896"></a>00896 <span class="preprocessor">#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL &lt;&lt; CoreDebug_DHCSR_S_RETIRE_ST_Pos)       </span>
<a name="l00898"></a>00898 <span class="preprocessor">#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             </span>
<a name="l00899"></a>00899 <span class="preprocessor">#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL &lt;&lt; CoreDebug_DHCSR_S_LOCKUP_Pos)          </span>
<a name="l00901"></a>00901 <span class="preprocessor">#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             </span>
<a name="l00902"></a>00902 <span class="preprocessor">#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL &lt;&lt; CoreDebug_DHCSR_S_SLEEP_Pos)           </span>
<a name="l00904"></a>00904 <span class="preprocessor">#define CoreDebug_DHCSR_S_HALT_Pos         17                                             </span>
<a name="l00905"></a>00905 <span class="preprocessor">#define CoreDebug_DHCSR_S_HALT_Msk         (1UL &lt;&lt; CoreDebug_DHCSR_S_HALT_Pos)            </span>
<a name="l00907"></a>00907 <span class="preprocessor">#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             </span>
<a name="l00908"></a>00908 <span class="preprocessor">#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL &lt;&lt; CoreDebug_DHCSR_S_REGRDY_Pos)          </span>
<a name="l00910"></a>00910 <span class="preprocessor">#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             </span>
<a name="l00911"></a>00911 <span class="preprocessor">#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL &lt;&lt; CoreDebug_DHCSR_C_SNAPSTALL_Pos)       </span>
<a name="l00913"></a>00913 <span class="preprocessor">#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             </span>
<a name="l00914"></a>00914 <span class="preprocessor">#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL &lt;&lt; CoreDebug_DHCSR_C_MASKINTS_Pos)        </span>
<a name="l00916"></a>00916 <span class="preprocessor">#define CoreDebug_DHCSR_C_STEP_Pos          2                                             </span>
<a name="l00917"></a>00917 <span class="preprocessor">#define CoreDebug_DHCSR_C_STEP_Msk         (1UL &lt;&lt; CoreDebug_DHCSR_C_STEP_Pos)            </span>
<a name="l00919"></a>00919 <span class="preprocessor">#define CoreDebug_DHCSR_C_HALT_Pos          1                                             </span>
<a name="l00920"></a>00920 <span class="preprocessor">#define CoreDebug_DHCSR_C_HALT_Msk         (1UL &lt;&lt; CoreDebug_DHCSR_C_HALT_Pos)            </span>
<a name="l00922"></a>00922 <span class="preprocessor">#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             </span>
<a name="l00923"></a>00923 <span class="preprocessor">#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL &lt;&lt; CoreDebug_DHCSR_C_DEBUGEN_Pos)         </span>
<a name="l00925"></a>00925 <span class="preprocessor"></span><span class="comment">/* Debug Core Register Selector Register */</span>
<a name="l00926"></a>00926 <span class="preprocessor">#define CoreDebug_DCRSR_REGWnR_Pos         16                                             </span>
<a name="l00927"></a>00927 <span class="preprocessor">#define CoreDebug_DCRSR_REGWnR_Msk         (1UL &lt;&lt; CoreDebug_DCRSR_REGWnR_Pos)            </span>
<a name="l00929"></a>00929 <span class="preprocessor">#define CoreDebug_DCRSR_REGSEL_Pos          0                                             </span>
<a name="l00930"></a>00930 <span class="preprocessor">#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL &lt;&lt; CoreDebug_DCRSR_REGSEL_Pos)         </span>
<a name="l00932"></a>00932 <span class="preprocessor"></span><span class="comment">/* Debug Exception and Monitor Control Register */</span>
<a name="l00933"></a>00933 <span class="preprocessor">#define CoreDebug_DEMCR_TRCENA_Pos         24                                             </span>
<a name="l00934"></a>00934 <span class="preprocessor">#define CoreDebug_DEMCR_TRCENA_Msk         (1UL &lt;&lt; CoreDebug_DEMCR_TRCENA_Pos)            </span>
<a name="l00936"></a>00936 <span class="preprocessor">#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             </span>
<a name="l00937"></a>00937 <span class="preprocessor">#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL &lt;&lt; CoreDebug_DEMCR_MON_REQ_Pos)           </span>
<a name="l00939"></a>00939 <span class="preprocessor">#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             </span>
<a name="l00940"></a>00940 <span class="preprocessor">#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL &lt;&lt; CoreDebug_DEMCR_MON_STEP_Pos)          </span>
<a name="l00942"></a>00942 <span class="preprocessor">#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             </span>
<a name="l00943"></a>00943 <span class="preprocessor">#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL &lt;&lt; CoreDebug_DEMCR_MON_PEND_Pos)          </span>
<a name="l00945"></a>00945 <span class="preprocessor">#define CoreDebug_DEMCR_MON_EN_Pos         16                                             </span>
<a name="l00946"></a>00946 <span class="preprocessor">#define CoreDebug_DEMCR_MON_EN_Msk         (1UL &lt;&lt; CoreDebug_DEMCR_MON_EN_Pos)            </span>
<a name="l00948"></a>00948 <span class="preprocessor">#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             </span>
<a name="l00949"></a>00949 <span class="preprocessor">#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL &lt;&lt; CoreDebug_DEMCR_VC_HARDERR_Pos)        </span>
<a name="l00951"></a>00951 <span class="preprocessor">#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             </span>
<a name="l00952"></a>00952 <span class="preprocessor">#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL &lt;&lt; CoreDebug_DEMCR_VC_INTERR_Pos)         </span>
<a name="l00954"></a>00954 <span class="preprocessor">#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             </span>
<a name="l00955"></a>00955 <span class="preprocessor">#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL &lt;&lt; CoreDebug_DEMCR_VC_BUSERR_Pos)         </span>
<a name="l00957"></a>00957 <span class="preprocessor">#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             </span>
<a name="l00958"></a>00958 <span class="preprocessor">#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL &lt;&lt; CoreDebug_DEMCR_VC_STATERR_Pos)        </span>
<a name="l00960"></a>00960 <span class="preprocessor">#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             </span>
<a name="l00961"></a>00961 <span class="preprocessor">#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL &lt;&lt; CoreDebug_DEMCR_VC_CHKERR_Pos)         </span>
<a name="l00963"></a>00963 <span class="preprocessor">#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             </span>
<a name="l00964"></a>00964 <span class="preprocessor">#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL &lt;&lt; CoreDebug_DEMCR_VC_NOCPERR_Pos)        </span>
<a name="l00966"></a>00966 <span class="preprocessor">#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             </span>
<a name="l00967"></a>00967 <span class="preprocessor">#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL &lt;&lt; CoreDebug_DEMCR_VC_MMERR_Pos)          </span>
<a name="l00969"></a>00969 <span class="preprocessor">#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             </span>
<a name="l00970"></a>00970 <span class="preprocessor">#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL &lt;&lt; CoreDebug_DEMCR_VC_CORERESET_Pos)      </span>
<a name="l00972"></a>00972 <span class="preprocessor"></span>
<a name="l00979"></a>00979 <span class="preprocessor"></span><span class="comment">/* Memory mapping of Cortex-M4 Hardware */</span>
<a name="l00980"></a>00980 <span class="preprocessor">#define SCS_BASE            (0xE000E000UL)                            </span>
<a name="l00981"></a>00981 <span class="preprocessor">#define ITM_BASE            (0xE0000000UL)                            </span>
<a name="l00982"></a>00982 <span class="preprocessor">#define CoreDebug_BASE      (0xE000EDF0UL)                            </span>
<a name="l00983"></a>00983 <span class="preprocessor">#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    </span>
<a name="l00984"></a>00984 <span class="preprocessor">#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    </span>
<a name="l00985"></a>00985 <span class="preprocessor">#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    </span>
<a name="l00987"></a>00987 <span class="preprocessor">#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   </span>
<a name="l00988"></a>00988 <span class="preprocessor">#define SCB                 ((SCB_Type       *)     SCB_BASE      )   </span>
<a name="l00989"></a>00989 <span class="preprocessor">#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   </span>
<a name="l00990"></a>00990 <span class="preprocessor">#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   </span>
<a name="l00991"></a>00991 <span class="preprocessor">#define ITM                 ((ITM_Type       *)     ITM_BASE      )   </span>
<a name="l00992"></a>00992 <span class="preprocessor">#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   </span>
<a name="l00994"></a>00994 <span class="preprocessor">#if (__MPU_PRESENT == 1)</span>
<a name="l00995"></a>00995 <span class="preprocessor"></span><span class="preprocessor">  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    </span>
<a name="l00996"></a>00996 <span class="preprocessor">  #define MPU               ((MPU_Type       *)     MPU_BASE      )   </span>
<a name="l00997"></a>00997 <span class="preprocessor">#endif</span>
<a name="l00998"></a>00998 <span class="preprocessor"></span>
<a name="l00999"></a>00999 <span class="preprocessor">#if (__FPU_PRESENT == 1)</span>
<a name="l01000"></a>01000 <span class="preprocessor"></span><span class="preprocessor">  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    </span>
<a name="l01001"></a>01001 <span class="preprocessor">  #define FPU               ((FPU_Type       *)     FPU_BASE      )   </span>
<a name="l01002"></a>01002 <span class="preprocessor">#endif</span>
<a name="l01003"></a>01003 <span class="preprocessor"></span>
<a name="l01008"></a>01008 <span class="comment">/*******************************************************************************</span>
<a name="l01009"></a>01009 <span class="comment"> *                Hardware Abstraction Layer</span>
<a name="l01010"></a>01010 <span class="comment"> ******************************************************************************/</span>
<a name="l01021"></a>01021 <span class="comment">/* ##########################   NVIC functions  #################################### */</span>
<a name="l01037"></a>01037 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<a name="l01038"></a>01038 {
<a name="l01039"></a>01039   uint32_t reg_value;
<a name="l01040"></a>01040   uint32_t PriorityGroupTmp = (PriorityGroup &amp; (uint32_t)0x07);               <span class="comment">/* only values 0..7 are used          */</span>
<a name="l01041"></a>01041 
<a name="l01042"></a>01042   reg_value  =  SCB-&gt;AIRCR;                                                   <span class="comment">/* read old register configuration    */</span>
<a name="l01043"></a>01043   reg_value &amp;= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             <span class="comment">/* clear bits to change               */</span>
<a name="l01044"></a>01044   reg_value  =  (reg_value                                 |
<a name="l01045"></a>01045                 ((uint32_t)0x5FA &lt;&lt; SCB_AIRCR_VECTKEY_Pos) |
<a name="l01046"></a>01046                 (PriorityGroupTmp &lt;&lt; 8));                                     <span class="comment">/* Insert write key and priorty group */</span>
<a name="l01047"></a>01047   SCB-&gt;AIRCR =  reg_value;
<a name="l01048"></a>01048 }
<a name="l01049"></a>01049 
<a name="l01050"></a>01050 
<a name="l01058"></a>01058 <span class="keyword">static</span> __INLINE uint32_t NVIC_GetPriorityGrouping(<span class="keywordtype">void</span>)
<a name="l01059"></a>01059 {
<a name="l01060"></a>01060   <span class="keywordflow">return</span> ((SCB-&gt;AIRCR &amp; SCB_AIRCR_PRIGROUP_Msk) &gt;&gt; SCB_AIRCR_PRIGROUP_Pos);   <span class="comment">/* read priority grouping field */</span>
<a name="l01061"></a>01061 }
<a name="l01062"></a>01062 
<a name="l01063"></a>01063 
<a name="l01071"></a>01071 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> NVIC_EnableIRQ(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251" title="STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...">IRQn_Type</a> <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083" title="STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...">IRQn</a>)
<a name="l01072"></a>01072 {
<a name="l01073"></a>01073 <span class="comment">/*  NVIC-&gt;ISER[((uint32_t)(IRQn) &gt;&gt; 5)] = (1 &lt;&lt; ((uint32_t)(IRQn) &amp; 0x1F));  enable interrupt */</span>
<a name="l01074"></a>01074   NVIC-&gt;ISER[(uint32_t)((int32_t)<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083" title="STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...">IRQn</a>) &gt;&gt; 5] = (uint32_t)(1 &lt;&lt; ((uint32_t)((int32_t)<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083" title="STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...">IRQn</a>) &amp; (uint32_t)0x1F)); <span class="comment">/* enable interrupt */</span>
<a name="l01075"></a>01075 }
<a name="l01076"></a>01076 
<a name="l01077"></a>01077 
<a name="l01085"></a>01085 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> NVIC_DisableIRQ(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251" title="STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...">IRQn_Type</a> IRQn)
<a name="l01086"></a>01086 {
<a name="l01087"></a>01087   NVIC-&gt;ICER[((uint32_t)(IRQn) &gt;&gt; 5)] = (1 &lt;&lt; ((uint32_t)(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083" title="STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...">IRQn</a>) &amp; 0x1F)); <span class="comment">/* disable interrupt */</span>
<a name="l01088"></a>01088 }
<a name="l01089"></a>01089 
<a name="l01090"></a>01090 
<a name="l01100"></a>01100 <span class="keyword">static</span> __INLINE uint32_t NVIC_GetPendingIRQ(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251" title="STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...">IRQn_Type</a> IRQn)
<a name="l01101"></a>01101 {
<a name="l01102"></a>01102   <span class="keywordflow">return</span>((uint32_t) ((NVIC-&gt;ISPR[(uint32_t)(IRQn) &gt;&gt; 5] &amp; (1 &lt;&lt; ((uint32_t)(IRQn) &amp; 0x1F)))?1:0)); <span class="comment">/* Return 1 if pending else 0 */</span>
<a name="l01103"></a>01103 }
<a name="l01104"></a>01104 
<a name="l01105"></a>01105 
<a name="l01113"></a>01113 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> NVIC_SetPendingIRQ(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251" title="STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...">IRQn_Type</a> IRQn)
<a name="l01114"></a>01114 {
<a name="l01115"></a>01115   NVIC-&gt;ISPR[((uint32_t)(IRQn) &gt;&gt; 5)] = (1 &lt;&lt; ((uint32_t)(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083" title="STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...">IRQn</a>) &amp; 0x1F)); <span class="comment">/* set interrupt pending */</span>
<a name="l01116"></a>01116 }
<a name="l01117"></a>01117 
<a name="l01118"></a>01118 
<a name="l01126"></a>01126 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> NVIC_ClearPendingIRQ(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251" title="STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...">IRQn_Type</a> IRQn)
<a name="l01127"></a>01127 {
<a name="l01128"></a>01128   NVIC-&gt;ICPR[((uint32_t)(IRQn) &gt;&gt; 5)] = (1 &lt;&lt; ((uint32_t)(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083" title="STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...">IRQn</a>) &amp; 0x1F)); <span class="comment">/* Clear pending interrupt */</span>
<a name="l01129"></a>01129 }
<a name="l01130"></a>01130 
<a name="l01131"></a>01131 
<a name="l01139"></a>01139 <span class="keyword">static</span> __INLINE uint32_t NVIC_GetActive(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251" title="STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...">IRQn_Type</a> IRQn)
<a name="l01140"></a>01140 {
<a name="l01141"></a>01141   <span class="keywordflow">return</span>((uint32_t)((NVIC-&gt;IABR[(uint32_t)(IRQn) &gt;&gt; 5] &amp; (1 &lt;&lt; ((uint32_t)(IRQn) &amp; 0x1F)))?1:0)); <span class="comment">/* Return 1 if active else 0 */</span>
<a name="l01142"></a>01142 }
<a name="l01143"></a>01143 
<a name="l01144"></a>01144 
<a name="l01156"></a>01156 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> NVIC_SetPriority(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251" title="STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...">IRQn_Type</a> IRQn, uint32_t priority)
<a name="l01157"></a>01157 {
<a name="l01158"></a>01158   <span class="keywordflow">if</span>(IRQn &lt; 0) {
<a name="l01159"></a>01159     SCB-&gt;SHP[((uint32_t)(IRQn) &amp; 0xF)-4] = ((priority &lt;&lt; (8 - <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)) &amp; 0xff); } <span class="comment">/* set Priority for Cortex-M  System Interrupts */</span>
<a name="l01160"></a>01160   <span class="keywordflow">else</span> {
<a name="l01161"></a>01161     NVIC-&gt;IP[(uint32_t)(IRQn)] = ((priority &lt;&lt; (8 - <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)) &amp; 0xff);    }        <span class="comment">/* set Priority for device specific Interrupts  */</span>
<a name="l01162"></a>01162 }
<a name="l01163"></a>01163 
<a name="l01164"></a>01164 
<a name="l01177"></a>01177 <span class="keyword">static</span> __INLINE uint32_t NVIC_GetPriority(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251" title="STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...">IRQn_Type</a> IRQn)
<a name="l01178"></a>01178 {
<a name="l01179"></a>01179 
<a name="l01180"></a>01180   <span class="keywordflow">if</span>(IRQn &lt; 0) {
<a name="l01181"></a>01181     <span class="keywordflow">return</span>((uint32_t)(SCB-&gt;SHP[((uint32_t)(IRQn) &amp; 0xF)-4] &gt;&gt; (8 - <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)));  } <span class="comment">/* get priority for Cortex-M  system interrupts */</span>
<a name="l01182"></a>01182   <span class="keywordflow">else</span> {
<a name="l01183"></a>01183     <span class="keywordflow">return</span>((uint32_t)(NVIC-&gt;IP[(uint32_t)(IRQn)]           &gt;&gt; (8 - <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)));  } <span class="comment">/* get priority for device specific interrupts  */</span>
<a name="l01184"></a>01184 }
<a name="l01185"></a>01185 
<a name="l01186"></a>01186 
<a name="l01201"></a>01201 <span class="keyword">static</span> __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
<a name="l01202"></a>01202 {
<a name="l01203"></a>01203   uint32_t PriorityGroupTmp = (PriorityGroup &amp; 0x07);          <span class="comment">/* only values 0..7 are used          */</span>
<a name="l01204"></a>01204   uint32_t PreemptPriorityBits;
<a name="l01205"></a>01205   uint32_t SubPriorityBits;
<a name="l01206"></a>01206 
<a name="l01207"></a>01207   PreemptPriorityBits = ((7 - PriorityGroupTmp) &gt; <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>) ? <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> : 7 - PriorityGroupTmp;
<a name="l01208"></a>01208   SubPriorityBits     = ((PriorityGroupTmp + <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>) &lt; 7) ? 0 : PriorityGroupTmp - 7 + <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>;
<a name="l01209"></a>01209 
<a name="l01210"></a>01210   <span class="keywordflow">return</span> (
<a name="l01211"></a>01211            ((PreemptPriority &amp; ((1 &lt;&lt; (PreemptPriorityBits)) - 1)) &lt;&lt; SubPriorityBits) |
<a name="l01212"></a>01212            ((SubPriority     &amp; ((1 &lt;&lt; (SubPriorityBits    )) - 1)))
<a name="l01213"></a>01213          );
<a name="l01214"></a>01214 }
<a name="l01215"></a>01215 
<a name="l01216"></a>01216 
<a name="l01231"></a>01231 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
<a name="l01232"></a>01232 {
<a name="l01233"></a>01233   uint32_t PriorityGroupTmp = (PriorityGroup &amp; 0x07);          <span class="comment">/* only values 0..7 are used          */</span>
<a name="l01234"></a>01234   uint32_t PreemptPriorityBits;
<a name="l01235"></a>01235   uint32_t SubPriorityBits;
<a name="l01236"></a>01236 
<a name="l01237"></a>01237   PreemptPriorityBits = ((7 - PriorityGroupTmp) &gt; __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
<a name="l01238"></a>01238   SubPriorityBits     = ((PriorityGroupTmp + <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>) &lt; 7) ? 0 : PriorityGroupTmp - 7 + <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>;
<a name="l01239"></a>01239 
<a name="l01240"></a>01240   *pPreemptPriority = (Priority &gt;&gt; SubPriorityBits) &amp; ((1 &lt;&lt; (PreemptPriorityBits)) - 1);
<a name="l01241"></a>01241   *pSubPriority     = (Priority                   ) &amp; ((1 &lt;&lt; (SubPriorityBits    )) - 1);
<a name="l01242"></a>01242 }
<a name="l01243"></a>01243 
<a name="l01244"></a>01244 
<a name="l01249"></a>01249 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> NVIC_SystemReset(<span class="keywordtype">void</span>)
<a name="l01250"></a>01250 {
<a name="l01251"></a>01251   __DSB();                                                     <span class="comment">/* Ensure all outstanding memory accesses included</span>
<a name="l01252"></a>01252 <span class="comment">                                                                  buffered write are completed before reset */</span>
<a name="l01253"></a>01253   SCB-&gt;AIRCR  = ((0x5FA &lt;&lt; SCB_AIRCR_VECTKEY_Pos)      |
<a name="l01254"></a>01254                  (SCB-&gt;AIRCR &amp; SCB_AIRCR_PRIGROUP_Msk) |
<a name="l01255"></a>01255                  SCB_AIRCR_SYSRESETREQ_Msk);                   <span class="comment">/* Keep priority group unchanged */</span>
<a name="l01256"></a>01256   __DSB();                                                     <span class="comment">/* Ensure completion of memory access */</span>
<a name="l01257"></a>01257   <span class="keywordflow">while</span>(1);                                                    <span class="comment">/* wait until reset */</span>
<a name="l01258"></a>01258 }
<a name="l01259"></a>01259 
<a name="l01264"></a>01264 <span class="comment">/* ##################################    SysTick function  ############################################ */</span>
<a name="l01270"></a>01270 <span class="preprocessor">#if (__Vendor_SysTickConfig == 0)</span>
<a name="l01271"></a>01271 <span class="preprocessor"></span>
<a name="l01281"></a>01281 <span class="keyword">static</span> __INLINE uint32_t SysTick_Config(uint32_t ticks)
<a name="l01282"></a>01282 {
<a name="l01283"></a>01283   <span class="keywordflow">if</span> (ticks &gt; SysTick_LOAD_RELOAD_Msk)  <span class="keywordflow">return</span> (1);            <span class="comment">/* Reload value impossible */</span>
<a name="l01284"></a>01284 
<a name="l01285"></a>01285   SysTick-&gt;LOAD  = (ticks &amp; SysTick_LOAD_RELOAD_Msk) - 1;      <span class="comment">/* set reload register */</span>
<a name="l01286"></a>01286   NVIC_SetPriority (<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a>, (1&lt;&lt;__NVIC_PRIO_BITS) - 1);  <span class="comment">/* set Priority for Cortex-M0 System Interrupts */</span>
<a name="l01287"></a>01287   SysTick-&gt;VAL   = 0;                                          <span class="comment">/* Load the SysTick Counter Value */</span>
<a name="l01288"></a>01288   SysTick-&gt;CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
<a name="l01289"></a>01289                    SysTick_CTRL_TICKINT_Msk   |
<a name="l01290"></a>01290                    SysTick_CTRL_ENABLE_Msk;                    <span class="comment">/* Enable SysTick IRQ and SysTick Timer */</span>
<a name="l01291"></a>01291   <span class="keywordflow">return</span> (0);                                                  <span class="comment">/* Function successful */</span>
<a name="l01292"></a>01292 }
<a name="l01293"></a>01293 
<a name="l01294"></a>01294 <span class="preprocessor">#endif</span>
<a name="l01295"></a>01295 <span class="preprocessor"></span>
<a name="l01300"></a>01300 <span class="comment">/* ##################################### Debug In/Output function ########################################### */</span>
<a name="l01306"></a>01306 <span class="keyword">extern</span> <span class="keyword">volatile</span> int32_t ITM_RxBuffer;                    
<a name="l01307"></a>01307 <span class="preprocessor">#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 </span>
<a name="l01319"></a>01319 <span class="preprocessor">static __INLINE uint32_t ITM_SendChar (uint32_t ch)</span>
<a name="l01320"></a>01320 <span class="preprocessor"></span>{
<a name="l01321"></a>01321   <span class="keywordflow">if</span> ((CoreDebug-&gt;DEMCR &amp; CoreDebug_DEMCR_TRCENA_Msk)  &amp;&amp;      <span class="comment">/* Trace enabled */</span>
<a name="l01322"></a>01322       (ITM-&gt;TCR &amp; ITM_TCR_ITMENA_Msk)                  &amp;&amp;      <span class="comment">/* ITM enabled */</span>
<a name="l01323"></a>01323       (ITM-&gt;TER &amp; (1UL &lt;&lt; 0)        )                    )     <span class="comment">/* ITM Port #0 enabled */</span>
<a name="l01324"></a>01324   {
<a name="l01325"></a>01325     <span class="keywordflow">while</span> (ITM-&gt;PORT[0].u32 == 0);
<a name="l01326"></a>01326     ITM-&gt;PORT[0].u8 = (uint8_t) ch;
<a name="l01327"></a>01327   }
<a name="l01328"></a>01328   <span class="keywordflow">return</span> (ch);
<a name="l01329"></a>01329 }
<a name="l01330"></a>01330 
<a name="l01331"></a>01331 
<a name="l01341"></a>01341 <span class="keyword">static</span> __INLINE int32_t ITM_ReceiveChar (<span class="keywordtype">void</span>) {
<a name="l01342"></a>01342   int32_t ch = -1;                           <span class="comment">/* no character available */</span>
<a name="l01343"></a>01343 
<a name="l01344"></a>01344   <span class="keywordflow">if</span> (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
<a name="l01345"></a>01345     ch = ITM_RxBuffer;
<a name="l01346"></a>01346     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       <span class="comment">/* ready for next character */</span>
<a name="l01347"></a>01347   }
<a name="l01348"></a>01348 
<a name="l01349"></a>01349   <span class="keywordflow">return</span> (ch);
<a name="l01350"></a>01350 }
<a name="l01351"></a>01351 
<a name="l01352"></a>01352 
<a name="l01361"></a>01361 <span class="keyword">static</span> __INLINE int32_t ITM_CheckChar (<span class="keywordtype">void</span>) {
<a name="l01362"></a>01362 
<a name="l01363"></a>01363   <span class="keywordflow">if</span> (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
<a name="l01364"></a>01364     <span class="keywordflow">return</span> (0);                                 <span class="comment">/* no character available */</span>
<a name="l01365"></a>01365   } <span class="keywordflow">else</span> {
<a name="l01366"></a>01366     <span class="keywordflow">return</span> (1);                                 <span class="comment">/*    character available */</span>
<a name="l01367"></a>01367   }
<a name="l01368"></a>01368 }
<a name="l01369"></a>01369 
<a name="l01372"></a>01372 <span class="preprocessor">#endif </span><span class="comment">/* __CORE_CM4_H_DEPENDANT */</span>
<a name="l01373"></a>01373 
<a name="l01374"></a>01374 <span class="preprocessor">#endif </span><span class="comment">/* __CMSIS_GENERIC */</span>
<a name="l01375"></a>01375 
<a name="l01376"></a>01376 <span class="preprocessor">#ifdef __cplusplus</span>
<a name="l01377"></a>01377 <span class="preprocessor"></span>}
<a name="l01378"></a>01378 <span class="preprocessor">#endif</span>
</pre></div></div><!-- contents -->


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